The present invention relates to logic circuits for high speed data transmission and more particularly to an improved double width data bus, single rate to single width data bus, double rate converter circuit operable with a single clock.
For any data output at double rate when a single clock is used, there is a problem of unmatched delay between data going out of the rising edge or the falling edge. When only one clock is available, it is common practice to use both the rising and the falling edges of the clock signal to double the data transmission speed. FIG. 1a illustrates the basic principle of generating two successive data, e.g. d0 and d1, within a period frame when only one clock signal is used, to double the data transmission rate. As known for those skilled in the art, the rising and falling edges of the output data need to be synchronous.
A trivial variant is based upon the use of this clock signal, referred to as the positive clock, and its inverted phase referred to as the negative clock. As apparent in FIG. 1b, the edges of the positive and negative clocks need to be synchronous. FIG. 2 shows a conventional circuit referenced 10 that implements this basic principle.
Now turning to FIG. 2, let us consider data d0 and d1 for the sake of illustration (the reasoning would be the same for the subsequent pairs of even data, d2, d4, . . . and odd data d3, d5, . . . and so on). Even and odd data are simultaneously transmitted to latches 11 and 12 as input data (the generation of these input data is not detailed). Latches 11 and 12 are driven by the positive and the negative clock signals that are generated by the clock tree and the inverted clock tree 13 and 13xe2x80x3 respectively. Let us assume that data d0 (also referred to as the positive data) and d1 (also referred to as the negative data) are sent on the double width bus 14 at single rate, then applied to multiplexor 15 driven by the main clock. Under control of multiplexor 15, data d0 and d1 are serially and alternatively sent on the single width output bus 16 at double rate for further processing. Block 17 schematically represents the standard circuits to generate the regenerated clock labeled Clock* upon which the output data d0 and d1 must be aligned. As apparent in FIG. 2, there are different paths for data d0 and d1 referred to as path#1 (positive edge path) and path#2 (negative edge path) respectively. A third path, path#3, which relates to the control of the multiplexor 15 is also of significance, the time necessary to switch from d0 to d1 is not equal to the reverse operation, i.e. to switch from d1 to d0. As a matter of fact, these paths have different output timings, and for each path, the output timing depends upon it is a rising or a falling edge. The worst path is unpredictable, since it can be either one of paths #1, #2 or #3 due to the multiplexor 15 which cannot be balanced. Another major problem lies in the timing analysis and testability of circuit 10 according to any scan-chain testability method, such as the LSSD (Level Sensitive Scan Design), because the presence of multiplexor 15. As a matter of fact, to use a clock as a data in the select input of multiplexor 15 is always a problem because there is no possibility to control it with the scan chain.
It is therefore a primary object of the present invention to provide an improved double width data bus, single rate to single width data bus, double rate converter circuit which does not require the use of a multiplexor but rather implements a balanced XOR function.
It is another object of the present invention to provide an improved double width data bus, single rate to single width data bus, double rate converter circuit that is fully testable and complies with any standard scan-chain based testability method.
It is another object of the present invention to provide an improved double width data bus, single rate to single width data bus, double rate converter circuit that offers identical paths to output data and thus fully synchronous output timings.
According to the present invention there is described a double width data bus, single rate to single width data bus, double rate converter circuit comprising: first and second data bus respectively transporting even data (d0, d2, d4, d6, . . . dn) and odd data (d1, d3, d5, d7, . . . , dn+1), wherein n (n=0, 2, . . . ) that are emitted at a single rate; clock generation means to generate a clock (positive clock) and its inverted phase (negative clock); means (20) for mixing said data dn and dn+1 to generate two intermediate data derived therefrom labeled dn mix for data dn and dn+1 mix for data dn+1 respectively; wherein dn mix results of the multiplexing of dn and not(dn) by mixed data dnxe2x88x921 mix on the rising edge of the positive clock and dn+1 mix results of the multiplexing of dn+1 and not(dn+1) by mixed data dnmix on the rising edge of the negative clock; means (21) for XORing mixed data dm mix and dm+1 mix to generate output data dm and for XORing mixed data dm+1mix and dm+2mix to generate output data dm+1 so that said output data dm and dm+1 can be transmitted on a single width bus at double rate; and, clock generation means to generate a clock (clock*) synchronous with said output data.
According to a major aspect of the present invention, the XORing function is performed exclusively with three two-way NAND gates according to relation: XOR(dmmix,dm+mix)=NAND(NAND (dmmix,dm+1mixinv),NAND(dmmixinv,dm+1mix)), wherein dmmixinv=not (dmmix) and dm+1mixinv=not(dm+1mix).
The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as other objects and advantages thereof, may be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings.